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Lead Physical Design Engineer at Netronome
Boxborough, MA, US

Description:

Netronome Systems is looking for a highly motivated individual to join our silicon design team.  In this position you will play a key role in the development of high-performance Network Processor SoCs, with duties in the back-end implementation process.   

Responsibilities:

The Lead Physical Design Engineer will have physical implementation responsibilities including:

 

Floorplanning, partitioning, P&R, timing, chip assembly and cleanup.

Contributing to synthesis/APR methodology and block implementation.  

Working closely with Architects and RTL Designers to ensure that requirements are well-understood, coordinated, and subsequently executed to deliver high quality silicon.

Requirements:

Bachelor or Master’s Degree in Electrical Engineering or Computer Science degree or equivalent.

6+ years of relevant experience. 

Experience with Fullchip Timing Closure, Constraint Generation and Maintenance and Timing Exceptions.

Experience implementing powergrid and clock tree at the chip level. Additionally verifying the correctness of these for EM/IR Drop.

Experience in the chip assembly, DRC/LVS cleanup and GDSII generation for tapeout.

Experience in partitioning and timing budgeting.

Experience in block synthesis and APR.

Solid understanding of hardware design fundamentals, computer and networking architecture and VLSI principles. 

Independent automation/parsing scripting experience in such languages as python/perl/tcl is required. Programming experience in C++/java/other is a plus.

Exposure to Verilog/VHDL coding and verification, CMOS circuits and digital design.

Must possess good interpersonal skills, be a quick learner and team player, and be ready to contribute wherever the need is.

Be able to quickly comprehend new challenges and plan the necessary tasks to meet overall objectives in a timely manner.

Good written and verbal communication skills and being able to deliver high quality output against deadlines are a must.