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Senior/Staff ASIC Design Engineer of AR/AI Project at VeriSilicon
Shanghai, CN

Senior/Staff ASIC Design Engineer of AR/AI Project

 

Descriptions:

Design top-of-the-line graphics/Vision processors, including specification, architecture, micro-architecture, implementation (using Verilog), and verification.

 

Requirements:

3+ years hands-on experience.

Programming skills in Verilog HDL.

Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation).

Highly motivated and skillful at solving difficult technical problems.

Knowledge of computer graphics and low-power design techniques is a plus.

Experience of OpenCL VX is a plus.

Experience of Neural Network and Tensor Processing design is a plus.

 

Location: Shanghai