Startup Careers

Be a part of our family by contributing to our portfolio companies’ innovation and success. Browse open positions below with Intel Capital portfolio companies.

Sr. Layout Engineer at VeriSilicon
Chengdu, CN

Sr. Layout Engineer



Design Mixed-Signal IP, RF IP and Foundation IP layout independently, including floor plan, power plan, parasitic extraction, physical verifications, document release and etc.

Generate and release tape-out kit.

Take charge of IP top layout and layout/PR design for IP test chip.

Mentor junior engineer.



BS degree or higher in EE, Physics or related majors. 

More than 4 years experiences in layout design. Experience in P&R is preferred.

Excellent knowledge on ESD, DFM, ERC, EM, IR and IC manufacturing process in deep sub-micron design. 

Experience in Synopsys/Cadence/Mentor EDA tools, skillful in scripting languages (Perl, Tcl, Shell) is a plus. 

Open minded, self-motivated, good communication skills and team work spirit, fluent in English.


Please send your resume to our Human Resources Department.