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RTL Design Engineer - Cache Subsystem at SiFive
Austin, TX, US
About SiFive

SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.

As the leading commercial provider of RISC-V processor IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our proven success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of domain-specific hardware needed to design next-generation products.

As a Cache Subsystem Microarchitect/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and cache subsystems, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

LOCATION: The person in this role can work out of our offices in the Bay Area, CA or Austin, TX. However, due to the current restrictions surrounding COVID-19, this position is work-from-home until further notice.


    Architect, design and implement new cache subsystems in SiFive's RISC-V CPU core generators and enhance features and performance in existing ones.
    Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
    Perform initial sandbox verification, and work with design verification team to create and execute detailed verification test plans.
    Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
    Collaborate with performance modeling team for performance exploration and optimization to meet performance goals.


    5+ yrs of recent industry experience in high-performance, energy-efficient CPU cache subsystem designs.
    Expertise in multi-level coherent CPU cache architectures and designs.
    Knowledge of RISC-V architecture is a plus.
    Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
    Experience with Scala and/or Chisel is a plus.
    Attention to detail and a focus on high-quality design.
    Ability to work well with others and a belief that engineering is a team sport.
    Knowledge of at least one object-oriented and/or functional programming language.
    Background of successful CPU cache subsystem development from architecture through tapeout.
    BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.