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RTL Design Engineer - RISC-V CPU at SiFive
HsinChu, TW
About SiFive
SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.

As the leading commercial provider of RISC-V processor IP & SoC IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our shown success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of domain-specific hardware needed to design next-generation products.

SiFive was founded and is actively run by the developers of RISC-V. If you are passionate about working with industry leaders and innovators, then send us your application today!

As a CPU Microarchitect/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

    Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
    Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
    Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
    Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
    Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.

Requirements

    2+ yrs of recent industry experience in high-performance, energy-efficient CPU designs.
    Experience with designing an out-of-order system ( high-performance DDR controller or caches controllers on a multicore system.)
    Expertise in CPU processor designs in one or more of the following areas is a plus: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; integer; floating-point, and vector units; load-store unit; cache and memory subsystems.
    Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL.
    Knowledge of at least one object-oriented and/or functional programming language.
    BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.
    Knowledge of RISC-V architecture is a plus.
    Experience with Scala and/or Chisel is a plus.
    Attention to detail and a focus on high-quality design.
    Ability to work well with others and a belief that engineering is a team sport.