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Compiler Engineer at SiFive
San Mateo, CA, US

 SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP & SoC IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our shown success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of domain-specific hardware needed to design next-generation products.

SiFive was founded and is actively run by the developers of RISC-V. If you are passionate about working with industry leaders and innovators, then send us your application today!

The SiFive Platform Engineering team is building an ambitious new infrastructure to support accelerated ASIC and FPGA design flows, IP delivery and SoC development - driving the next generation of SiFive's "Silicon at the speed of Software" mission. This infrastructure leverages state of the art compiler algorithms (built on open source MLIR and LLVM technologies), novel build system integration, and new Verilog RTL generation techniques.

Our team combines many different perspectives and experiences, and we love working with people who combine a passion for learning and growth with product focus, practical experience, and a desire to build world-changing technologies.

We encourage applicants from traditionally underrepresented groups in computer science to apply!

LEVEL: Please note that we are hiring for several positions on the Compiler Engineering team, and as such invite everybody with at least 2 years of Compiler Engineering experience to apply.


        Evolve, design and build new compiler intermediate representations for hardware design and tool flows.
        Implement specific compiler optimization and lowering algorithms for chip design flows.
        Implement state of the art mechanisms for hierarchical caching that crosscut compiler and build systems.
        Participate in design discussions, planning, code review, documentation, open source processes, and other standard software practices.
        Collaborate with hardware architects to develop the approach and design flows.
        Manage your individual project priorities, deadlines and deliverables.


        We are hiring for several positions with different levels of seniority, but require a minimum of 2 years of compiler engineering experience.
        Strong oral and written communication skills, excellent team collaboration.
        Experience with C++ programming and git-based development workflows.
        Experience with Verilog and other chip design technologies is NOT required.