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Verification Engineer at SiFive
San Mateo, CA, US

About SiFive

SiFive is an idea-to-silicon company founded by the inventors of RISC-V to simplify the design and production of custom SoCs.
As the leading commercial provider of RISC-V processor IP & SoC IP, SiFive is on a mission to help engineers design custom chips for domain-specific solutions for many markets, including 5G, edge AI, enterprise networking, storage, and consumer devices.

Industry-leading innovators, including six of the top ten semiconductor companies, are working with SiFive thanks to our shown success, deep expertise, and rich partner ecosystem. With SiFive’s rich IP ecosystem and accessible design platform, every market has access to the development of domain-specific hardware needed to design next-generation products.

SiFive was founded and is actively run by the developers of RISC-V. If you are passionate about working with industry leaders and innovators, then send us your application today!


As an experienced Verification Engineer on the Design Verification team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our verification quality of results. This verification position is a highly visible role, the simple purpose of which is to ensure the silicon works.

What will you work on when you join our team? By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.

LOCATION: The person in this role can work out of our offices in the Bay Area, CA or Austin, TX. However, due to the current restrictions surrounding COVID-19, this position is work-from-home until further notice.

Responsibilities

        Understand CPU and SoC designs from an architectural level and create effective verification strategies for these designs.
        Create test plans and test environments.
        Develop tools, test benches, and test suites (UVM, C++/C or otherwise, as needed) to execute test plans.
        Develop checkers and assertions to verify the design.
        Write functional coverage, analyze both code and functional coverage, and close coverage holes.
        Collaborate closely with the design team on feature specifications, test plans and failure analysis.

Requirements

        7+ years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, System Verilog, Verilog, Makefiles, scripting languages, etc.).
        Solid understanding of CPU and SoC architectures, or a strong desire and ability to learn same.
        A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, coverage analysis and closure).
        Verification experience in test planning, constrained random test generation, test stimulus, code coverage, functional coverage.
        Excellent debug skills.
        Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.).