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Senior/Staff Verification Engineer at VeriSilicon Holdings
Chengdu, CN


Focus on analog/digital mixed IP and Chip verification. The engineers need to act as a strong team member and contributor, who also need to collaborate with digital F.E team closely.

    Understanding the expected functionality of designs.

    Developing testing and regression plans.

    Designing and developing verification environment.

    Running RTL and gate-level simulations/regression.

    Code/functional coverage development, analysis and closure.


    Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).

    Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…).

    Familiar with design and verification languages (Verilog, System Verilog, SVA etc.).

    Scripting and automation skills (tcl, perl, makefile etc) is a plus; Familiar with C/C++ is a plus.

    Knowledge of USB/PCIE/MIPI, ARM based SOC and design experience is a plus.

    Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills.

    Independent and self-managing.