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Sr. Engineer of Analog SerDes PHY Design at VeriSilicon Holdings
Shanghai, CN


    Develop challenging analog circuits independently, including circuit design, simulation, testing, debugging and improvement.

    Determine system requirement, define project specifications according to customer’s requirement.

    Lead the project development.

    Contribute phenomenally to problem solving in circuit design, testing and debugging.

    Supervise layout development.

    Provide technical support for Customer/FAE/Sales.


    Master degree or above in EE.

    With 2+ years of work experience in analog and SerDes design.

    Experience with the architecture design and production of LVDS RX/TX ,HDMI RX/TX,or DP RX/TX.

    Experience with PLL, CDR, RX, TX or Equalizer design in deep-submicron CMOS.

    Experience with SerDes PHY circuit design.

    Experience with USB3.0, HDMI, MIPI, Display Port and PCI Express Transceiver.

    Fluent in both English and Chinese.

    Self motivated, good communication skill and team work spirit.