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FPU Design Engineer at SiFive
San Mateo, CA, US / Portland, OR, US / Austin, TX, US
SiFive is looking for hardware engineers who are passionate about designing industry leading CPUs to help drive the tidal wave of adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of vertical applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly configurable generators. We're leveraging technology and ideas from the software industry to execute hardware design with the agility of software development.
We build and maintain multiple CPU lines using the Chisel hardware construction library embedded in the Scala language, and are seeking motivated individuals to enhance our existing CPU lines as well as develop new ones. 
Join us, and surf the RISC-V wave with SiFive!

The Challenge

    • Designing the best CPU cores in the world, based on the revolutionary open RISC-V architecture;
    • Mastering the art of designing hardware as configurable generators in a hardware-enhanced software language;
    • Working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.


    • Architect, design and implement enhanced and new floating-point arithmetic functional units for RISC-V CPU Core generators in Chisel;
    • Create more efficient shared arithmetic units, combining capabilities for single/double/half-precision floating point, integer, and/or fixed-point operations;
    • Design in extensive configurability as a first-class consideration“Plumb” new design content into the SiFive’s Chisel/FIRRTL framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software;
    • Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans;
    • Ensure that knowledge is shared via great documentation and a participation in a culture of collaborative design.

What you bring to the challenge

    • Knowledge of CPU architecture;
    • Prior experience designing high-performance floating point units;
    • Proficiency with hardware (RTL) design in Verilog, System Verilog, or VDHL;
    • Attention to detail and a focus on high-quality designAbility to work well with others and a belief that engineering is a team sport;
    • Knowledge of at least one object-oriented and/or functional programming language;
    • BS/MS in EE, CE, CS or a related technical discipline, or equivalent experience.

Nice to have

    • Experience with Scala and/or Chisel
    • Knowledge of RISC-V architecture
    • Experience with Git/Github, Jira, Confluence