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DFT Engineer at SiFive
San Mateo, CA, US / Portland, OR, US / Austin, TX, US
We are automating the design process to democratize access to silicon. As a Design For Test Engineer in the Implementation Methodology group, you will help establish a DFT flow that will be used by different Design teams worldwide. We need out-of-the-box thinking to automate the whole Design For Test flow. This is an opportunity not only to work on all aspects of DFT, but also to work on its automation.

The Challenge

    • Help design a robust design for test methodology;
    • Help develop different Memory BIST and scan solutions;
    • Improve test coverage and DFT simulations;
    • Develop tool flows used by engineers in different design teams;
    • Work with Physical Designers on timing constraints;
    • Join us as we create a fully automated online chip design methodology.

What you bring to the challenge

    • A minimum of 5 years of experience with DFT;
    • Experience in scan and Memory BIST insertion and simulation;
    • Knowledge of using ATPG to improve test coverage;
    • Experience with DFT Design Rule Check tools;
    • Strong TCL software development skills;
    • Good written and verbal communication skills.

Education requirements

    • Master’s degree required with emphasis in Electrical Engineering, Computer architecture, or Computer Science
SiFive is proud to be an equal employment opportunity workplace. We offer a competitive compensation package that includes flexible paid time off, health, vision and dental benefits, 401(k) plan, employee stock option program, and much more. If you yearn to be challenged and wish to work in an environment where the boundaries of your creativity and skills will be tested, then SiFive is place for you.