Startup Careers

Be a part of our family by contributing to our portfolio companies’ innovation and success. Browse open positions below with Intel Capital portfolio companies.

Senior DFT(Design for Test) Engineer at VeriSilicon
Chengdu, CN
Descriptions:
  • Complete DFT test plan definition.
  • Complete DFT logic design, including: memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing.
  • Complete DFT test pattern verification.
  • Complete DFT mode timing constraint, support DFT mode timing closure.
  • Support chip bring-up, complete test pattern debugging, yield improvement.
  • Provide technical support for customer/FAE/sales.
 
Requirements:
  • Master of EE, 2+ years DFT work experiences or Bachelor of EE, 5+ years DFT work experiences.
  • Have following experiences: test plan definition, memory BIST, memory BISR, scan insertion, boundary scan insertion, macro testing logic design and verification, analyze ATE test pattern failure and perform diagnose.
  • Have back-end Synthesis, P&R, STA experiences is a plus.
  • Be able to skillfully use the Mentor/Synopsys DFT EDA tools.
  • Full of enterprise and the spirit of teamwork, good ability to communicate and express, fluent in Mandarin and English.