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Engineer/Sr. Engineer of ZSP Design Verification at VeriSilicon
Chengdu, CN
Descriptions:
  • Develop environments for ZSP system functional verification.
  • Write verification plans for ZSP system level IPs and systems.
  • Develop verification environments for IP and systems using C, verilog, Assembly, SystemVerilog, etc.
  • Contribute improvements to verification methodologies, and toolsets.
  • Develop script for verification flow with Python, Perl, etc.
 
Requirements:
  • 3-8 years working experience. BS/MS/PhD in Electrical/Computer Engineering.
  • Strong coding skills - using languages: Verilog, SystemVerilog, Perl, assembly, C++, C, Linux.
  • Great debugging and problem isolation skills.
  • AXI, AHB interconnect.
  • Computer architecture, memory subsystems.
  • Implementing verification methodologies including constrained random verification, coverage closure, Assertion Based Verification, Universal Verification Methodology.
  • Background knowledge for DSP, CPU, Cache is better.