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FPGA Design Engineer at Ossia
Bellevue, WA, US

Be on the forefront of a new, ground-breaking technology: Cota™ wireless power. Spearheaded by a team of highly experienced business leaders and specialized engineers, Ossia offers a once-in-a-lifetime opportunity to build one of the most highly anticipated technologies of our time. Countless devices across the globe will one day use our safe and smart power solutions. You will feel great about creating new and clean technology that helps people stay “always on and always connected.” Our employees are the key to our success and we are fortunate to have found some of the best and the brightest. There isn’t a more inspiring team to work with and no better time to join than now!

The Role:

Ossia is looking for an RTL design and/or RTL verification engineer to work on FPGA/ASIC micro-architecture designs, implementations, simulations, synthesis, verification, lab integration and board planning and bring-up. The focus of the work will be FPGA/ASICs and digital logic implementation and simulation.

Responsibilities include:

  • Design digital blocks for FPGA/ASICs, develop synthesizable Verilog/VHDL to implement the timing critical functionality and verifications.
  • Develop simulation flow, test bench, test cases, reference model, coverage model and automation (UVM/OVM experience is highly desirable).
  • Perform simulations and functional/timing analysis.
  • Work on lab bring-up and testing of FPGA boards and multi-board systems.
  • Interface with the Software team, Hardware team, RF team, Lab team, and Leadership & Marketing groups to ensure proper system feature set and integration.
  • Understanding of electronics lab equipment (Oscilloscope, Logic Analyzer, Spectrum Analyzer and In-Circuit Logic Analyzers) for testing.
  • Most critically, the ideal candidate will be able to prioritize multiple requests in a fast-paced environment with impeccable attention to detail and accuracy while maintaining a pleasant and "can do" attitude.


  • At least 5 years of experience (or 3 with Masters) in digital design and verification, implementation, and integration of FPGAs and/or ASICs.
  • Experience with Questa ModelSim, Xilinx Vivado, SystemVerilog and UVM/OVM methodology.
  • Design skills include architectural definition and development, state machine design, clock domain crossing methods, and external device interfaces (such as I2C, SPI, UART).
  • Practical knowledge of ASIC design, methodology, and flow as well as experience converting existing FPGA designs to ASIC technology is highly desirable.
  • Must be able to understand the requirements, architect a solution targeting an FPGA/ASIC against those requirements, and implement/verify/validate the solution.
  • Must be able to simulate the RTL to verify functionality and performance, then integrate and test the design on boards.
  • Experience defining timing constraints and achieving timing closure on complex FPGA/ASIC designs.
  • Experience with FPGA/ASIC test plan development and implementation is highly desirable.
  • Experience writing scripts in control languages such as: TCL, DOS Batch, Linux BASH, Perl, Python, etc.
  • Must be a US citizen or otherwise authorized to work in the US and in the process of green card application.


  • A BS or MS degree in EE, CE, or CS is required.