Startup Careers

Be a part of our family by contributing to our portfolio companies’ innovation and success. Browse open positions below with Intel Capital portfolio companies.

SENIOR ASIC Design Engineer at Tibit Communications
Petaluma, CA, US

BSEE, MS/PhD preferred 7+ years ASIC design experience. Solid experience with RTL design using Verilog 2-3 years +FPGA synthesis and design experience. Excellent written and verbal communications skills. Experience with modern SoC design architectures, ARM/MiPs type processor cores, Ethernet, Networking, and Data Communications. Strong debug and lab experience. Able to work under minimal supervision. Enjoys working in start-up environment.

Responsibilities

  • Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
  • Perform RTL coding, function/performance simulation debug, Lint/CDC/FV/UPF checks
  • Participate in synthesis, timing/power closure and FPGA/silicon bring-up
  • Participate in test plan and coverage analysis of the block and SOC-level verification

Minimum qualifications

  • BS degree in Electrical Engineering or equivalent practical experience
  • 5 years of practical experience
  • Experience in ASIC development with Verilog
  • Experience with ASIC design verification, synthesis, timing/power analysis and DFT

Preferred qualifications

  • MS degree in Electrical Engineering. 7+ years of practical experience
  • Knowledge of high performance and low power design techniques
  • Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture
  • Knowledge of assertion-based formal verification
  • Proficient with a scripting language like Perl

Please send cover letter and resume with “Job Application” as the subject.