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System Verification Engineer (UVM) at Montage Technology
Shanghai, CN

Job Description:

Participate ASIC digital verification for various IP/SoC projects;

Create verification plans with designers;

Develop DV architecture and verification environment;

Verification execution and sign-off.


Excellent team work style;

Solid IP/SoC verification background;

Mass production for verified IP/SoC;

Bachelor with minimum 2 years of working experience in ASIC digital verification;

Production experience in verification strategies and test plans;

Familiar with System Verilog/UVM for test bench creation, debug, reuse, constrained-random stimulus and functional coverage;

Production experience in ARM buses, such as AXI/AMBA/APB;

Familiar with verification tools;

Familiar with Linux, csh/Python or other script languages;

Good English reading and writing skills.