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Sr. Digital Dedign Engineer at Montage Technology
Shanghai, CN

Write micro-architecture definition and design implementation Spec;

Write RTL coding for block or top level;

Do IP level synthesis/timing analysis/formality check/CDC check/Code coverage check;

Assist verification engineers to complete module and top level simulation and verification;

Debug RTL/Gate Level waveform at module or top level;

Do Silicon debugging of the related module functionalities and provide ECO solution accordingly.


MSEE with 5-6 years of experience in digital design;

Relevant experience in high speed IO IP design, and PCIe design experience is a big plus;

Very strong skills in Verilog RTL coding, simulation debug and base or metal layer ECO;

Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc.;

Strong skills in Script and be familiar with TCL, Perl, etc.;

Self-motivated, good team work spirit and good communication skills.

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