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DFT Architect at SiFive
San Mateo, CA, US
SiFive is the leading provider of market-ready processor core IP, development tools and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors.
As a DFT Architect in the Implementation group, you will single-handedly lead the Design For Test on several SOC projects and shape the company-wide methodology to significantly scale the number of designs.
This is not only an opportunity to lead the Design For Test of an SoC, it’s an opportunity to shape the company-wide DFT methodology 
Our innovative and experienced team is scaling the number of Designs in an unprecedented way and we need out-of-the-box thinking, creating a path-breaking opportunity for a leading DFT expert to join our team. We are automating the Design process to democratize access to Silicon. You will enable non-DFT experts to not only insert scan and Memory BIST, but also generate and simulate patterns. Step up and join us in this revolution.

The Challenge

  • Lead the top-level Design For Test for several System On Chips
  • Help design a robust Design For Test methodology 
  • Deploy new DFT methodologies to company sites across the world

What you bring

  • A bare minimum of 8 years of recent experience with DFT
  • Experience managing all aspects of Design For Test for a System On Chip: scan, MBIST, 3rd party IP integration
  • Expertise in DFT IP reuse: IEEE 1500, core wrapping
  • Strong understanding of scan and BIST timing constraints
  • Thorough knowledge of the RTL to GDS implementation flow

Education / Certifications

  • Master’s degree required with emphasis in Electrical Engineering, Computer architecture, or Computer Science