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Design for Test Engineer at Syntiant
Irvine, CA, US

Member of Technical Staff position responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design.

  • Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow.

  • Excellent knowledge of latest state-of-the-art trends in DFT and test.

  • Hands-on experience with Jtag protocols, Scan and BIST architectures, including memory BIST, IO BIST

  • Verification skills include, System Verilog, UVM, Logic Equivalency checking and validating the Test-timing of the design.

  • Experience working with Gate level simulation, and debug with VCS and other simulators.

  • Working with Cadence Modus flow is a plus

 

Minimum qualification

  • MS degree in EE, 5+ years relevant experience in DFT