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Verification Engineer at Syntiant
Irvine, CA, US

Member of Technical Staff position is for experienced SoC verification engineer responsible for pre-silicon RTL verification at the block and top-level SoC.  

  • Expertise in HDL languages, Verilog and SystemVerilog, SystemC is desired

  • Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy

  • Solid verification skills in problem solving and debugging

  • Programming experience in C/C++ as well as Python

  • Exposure to UVM is desired

  • Work on HW/SW emulation platforms

 

Minimum qualification

  • MS degree in EE, 5+ years relevant experience in SoC verification