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Design Verification Engineer at Netronome
Boxborough, MA, US
Netronome Systems, Inc. seeks a Design Verification Engineer to work in their Boxborough, MA office to create verification test plans for chip design units based on architectural/design specifications and understanding of the intended behavior of the chip design elements.  
Responsibilities:
  • Create verification test benches from unit level testing up to full-chip testing based on assigned design block.  
  • Develop new System Verilog components from bus functional models to test sequences as required by their testbench.  
  • Write tests and test sequences that check the correct operations of the design block.  
  • Debug and design logic Register Transfer Level ("RTL") to find the root cause of any failing tests.  
  • Write functional coverage cover points to confirm that all intended elements of the design were tested.  
  • Bring testing to final closure of complete functional coverage.  
Requirements:
Must have a Master's degree (or foreign equivalent) in Computer or Electrical Engineering, or a directly related field. Will also accept a Bachelor's degree (or foreign equivalent) in Computer or Electrical Engineering or a directly related field of study plus five (5) years of post-baccalaureate/progressively responsible design engineering experience in a directly related position.
 
 
Must know (from any completed university-level coursework, seminars, workshops, or real-world, hands-on experience): 
  • Design verification and simulation practices, including identifying the proper valid items to test; 
  • Developing Design Verification test benches to perform simulation and testing; 
  • Hardware interfaces and protocols, including I2C;  
  • C software language; 
  • VHDL hardware language in Linux environment; and 
  • Computer architecture and engineering networking architecture, including microcontrollers.